1. Field of the Invention
The present invention relates to a semiconductor element layout method, and particularly, to a method of laying out contacts and substrate contacts through process migration to form a new mask layout according to existing layout resources.
2. Description of the Prior Art
Process migration involves scaling, layer operation, and compaction to convert an existing mask layout prepared for integrated circuits according to a design rule into a new mask layout that follows a different design rule. There are two methods to carry out the process migration.
One is a simple scaling method (hereinafter referred to as the first prior art). This method simply scales down an existing mask layout, grows or shrinks each layer of the scaled-down layout, and forms a new mask layout.
FIGS. 1A, 1B, and 1C show layouts according to the first prior art. Each layout involves a contact 111, a diffusion layer 112, and an aluminum layer 113. The contact 111 is a substrate contact, which is connected to substrate potential, e.g., grounding potential as shown in FIG. 2. The substrate contacts are properly arranged in a layout of semiconductor circuits, to stabilize the operation thereof.
The layout of FIG. 1A is an original mask layout including the substrate contact 111. The layout of FIG. 1B is formed by scaling down the layout of FIG. 1A at a magnification of 0.5. The layout of FIG. 1C is formed by growing only the substrate contact 111 of FIG. 1B.
The first prior art keeps the shapes and relative positions of elements before and after the process migration. For example, a first element on the right of a second element in an original layout is still on the right of the second element in a new layout.
The other method of achieving the process migration is a symbolic compactor method (hereinafter referred to as the second prior art). This method is disclosed in Japanese Laid-Open Patent Publication No. 63-159980. The second prior art forms a symbolic layout shown in FIG. 3A from an existing mask layout. The symbolic layout involves symbols that represent circuit elements. In FIG. 3A, a symbol 114 represents a substrate contact, and a straight segment symbol 115 represents an aluminum wiring layer. These symbols are simply scaled down, and spaces between the symbols are reduced by a symbolic compactor, to form a layout of FIG. 3B.
The second prior art sometimes changes the relative positions of elements and the shapes of wires before and after the process migration. Contacts and substrate contacts are unchanged before and after the process migration. If symbols overlap one upon another after the process migration, the second prior amalgamates the symbols and reduces the number thereof.
The first and second prior arts have the following problems:
(1) FIG. 4A shows an original mask layout, and FIG. 4B shows a new mask layout converted from the original mask layout according to the first or second prior art. The difference between the original and new layouts causes a loss area.
In FIG. 4A, an element region 121 is longer than a substrate contact 122, and an object 123 is adjacent to them. In FIG. 4B, a substrate contact 122a is longer than an element region 121a, and an object 123a is adjacent to them.
The difference between the layouts of the FIGS. 4A and 4B is caused by the difference between the design rules thereof. Compared with the original mask layout, the converted mask layout is narrower in gate intervals and wider in contact intervals. In FIG. 4B, it is impossible to move the object 123a to the left, to thereby produce a loss area, i.e., a dead space 124. The first prior art causes a larger loss area than the second prior art.
(2) The second prior art is superior to the first prior art in terms of the area loss. The second prior art, however, has a substrate contact problem.
To avoid the dead space caused by substrate contacts, it is preferable to neglect a contact spacing rule when carrying out symbolic compaction on a layout. Namely, it is preferable to carry out compaction without regard to a minimum spacing rule for contacts, if the contacts are in the same net, like substrate contacts connected to the same power source, because there will be no problem even if adjacent elements in the same net are short-circuited to each other. If a space narrower than a minimum space is produced by compaction, the space is closed later. This technique is effective to reduce a layout area.
This technique, however, raises a problem. In FIG. 5, substrate contacts 131 are too close to each other, and therefore, form an overlapped part 132. The overlapped part 132 violates a contact spacing rule or a contact minimum width rule. This violation corresponds to a DRC error occurring between objects in the same net. This sort of DRC error is one of the difficult problems of compaction, and there is no general solution for the problem. Most DRC errors in the same net are caused by violation of rules related to substrate contacts. A measure to cope with this problem is needed.
The most important issue in compaction is a large scale process. A practical solution for the large scale process is divisional compaction disclosed in Japanese Patent Application No. 4-253183. The divisional compaction divides a symbolic layout into sections, and compacts each of the sections. When dividing a symbolic layout into sections, the substrate contact problem occurs. The symbolic layout to be divided must have a space where neither contacts nor transistors are present. An area where circuit elements are formed has a sufficient space because the circuit elements are not always short-circuited to one another. An area where substrate contacts are formed, however, has no free space and is hardly divided into sections because the substrate contacts are usually arranged densely with no gap among them.
(3) When a layout is compacted without regard to a contact spacing rule, substrate contacts may overlap one upon another on the layout to cause a shortage of contact area. If a process vulnerable to a latch-up phenomenon is employed, the first and second prior arts will cause a shortage of substrate contacts.
(4) The first and second prior arts are not adaptable to new design rules.